1. Field of the Invention
The present invention relates to a semiconductor memory device having at least two layers of bit lines.
2. Description of the Background Art
In recent years, a T-shaped bit line configuration formed of at least two layers of bit lines has been employed in semiconductor memory devices, especially in static random access memories (SRAM). Such a configuration is disclosed, for example, in Japanese Patents Laying-Open Nos. 4-228188 and 7-183396.
FIG. 11 shows configurations of a memory cell array and its peripheral circuits of a semiconductor memory device, which is essentially identical to FIG. 13 of Japanese Patent Laying-Open No. 7-183396.
Referring to FIG. 11, memory cells 1a-1c are partitioned by a broken line. Note that this line is only shown in the drawing for convenience, and there is no such partition in an actual product. FIG. 11 includes squares other than memory cells 1a-1c. These squares, identical to memory cells 1a-1c but having no reference characters, also show memory cells. Likewise, for other patterns representing various components through the drawings, those having the same shapes represent the same components, and only representative members are labeled for purposes of presentation.
Bit lines in the first layer (hereinafter, first-layer bit lines) 2a and 2b are connected to the same memory cell, forming a bit line pair. Both bit lines 2a and 2b are also connected to bit line peripheral circuits 4a and 4c.
A word line 3 is connected to memory cells 1a, 1c, . . . , and to a row decoder 5. Of the bit lines in the second layer (hereinafter, second-layer bit lines) 22a and 22b, bit line 22a is connected via a contact hole 12a to first-layer bit line 2a, and bit line 22b is connected via a contact hole 12b to first-layer bit line 2b. Both bit lines 22a and 22b are connected to a bit line peripheral circuit 4b.
Generally, the direction along which first-layer bit lines 2a, 2b extend is called a column direction, while the direction along which word line 3 extends is called a row direction. Memory cells are arranged in the row and column directions, forming a memory cell array.
FIG. 12 shows memory cells within the memory cell array corresponding to a region A of FIG. 11, with three memory cells in the row direction and two memory cells in the column direction being selected. FIG. 12 illustrates the pattern of the bit lines in the first and second layers.
Memory cell regions 31a-31c include first-layer bit lines 32a-32d formed of a first metal interconnection layer, and second-layer bit lines 52a, 52b formed of a second metal interconnection layer. Second-layer bit lines 52a, 52b are connected via through-holes 42a, 42b as contact holes, to firstlayer bit lines 32a, 32b, respectively. Through-holes 42a and 42b are provided in respective memory cell regions 31a and 31b.
FIG. 13 illustrates an example of a memory cell pattern commonly used in an SRAM. Specifically, FIG. 13 shows the memory cell pattern located underneath the first-layer bit lines, corresponding to memory cell region 31a of FIG. 12.
This memory cell pattern includes: separating insulation films 61a-61c; active layers 62a-62j; layers including polycrystalline silicon (hereinafter, referred to as "polysilicon layers") 63a-63c; third metal interconnection layers 65a-65d; and first contacts 64a-64d coupling active layers 62a-62j and third metal interconnection layers 65a-65d.
Here, metal interconnection layer 65a is a GND interconnection, and metal interconnection layer 65b is a Vcc interconnection. First contacts 64a, 64b are called GND contacts, and first contacts 64c, 64d are called Vcc contacts. Further, this memory cell pattern includes: a first contact 64e connecting the polysilicon layer and the third metal interconnection layer; and second contacts 66a, 66b connecting first-layer bit lines 32a, 32b and active layers 62a, 62b, respectively. Second contacts 66a, 66b are herein called bit line contacts.
Active layers 62b, 62e, 62g and 62i are the layers storing memory data of the memory cell. Active layers 62b and 62g are connected by third metal interconnection layer 65c, thereby forming one storage node portion. Active layers 62e and 62i are connected by third metal interconnection layer 65d, thereby forming the other storage node portion.
Active layers 62c, 62f are the layers connected via GND contacts 64a, 64b to GND interconnection 65a. Thus, they are called the GND active layers. Active layers 62h, 62j are connected via Vcc contacts 64c, 64d to Vcc interconnection 65b, and thus called the Vcc active layers. Polysilicon layer 63a corresponds to word line 3 of FIG. 11.
Generally, memory cell regions have no boundary therebetween in an actual semiconductor memory device, and therefore, various definitions of boundaries can be considered. In any case, a memory cell region is a region which normally stores data of one bit.
Here, the size of the memory cell region in the row direction is defined as a minimal distance between the contact centers of GND contacts 64a and 64b taken in the row direction. It is specifically shown as CO in FIG. 13. The size of the memory cell region in the column direction is defined as a minimal distance between the contact center of bit line contact 66a or 66b and the center line of Vcc interconnection 65b.
In the case of FIG. 12, the size of the memory cell region in the row direction can be defined as the distance from the midpoint of bit lines 32a and 32c to the midpoint of bit lines 32b and 32d.
In the conventional memory cells as shown in FIGS. 12 and 13, the size of the memory cell region in the row direction is normally limited by the size of the pattern underneath the first-layer bit lines.
However, if the miniaturization of the pattern underneath the first-layer bit lines advances beyond the miniaturization of the pattern of the metal interconnection layers, it is expected that the size of the memory cell region will be limited by the size of the first-layer bit lines.
In particular, in memories required to operate with even higher speed or system LSI devices incorporating logic and memories in the coming age, the double layered bit line configurations will be widely used. Thus, there is a high possibility that the bit lines in the first and second layers may limit the memory cell size.
Specifically, the size of the memory cell in the row direction may be affected or limited by the size of the portion connecting the bit lines in the first and second layers. FIGS. 14 and 15 illustrate possible examples thereof.
To explain the limitation as described above in more detail, assume that the boundary of the memory cell regions in the row direction is defined as follows.
For the first memory cell and the second memory cell adjacent to each other in the row direction, their boundary is a line which passes the midpoint of the minimal gap between edges of a first-layer bit line in the first memory cell and a first-layer bit line in the second memory cell, and extends parallel to the column direction of the memory cell array.
Specifically, with reference to FIG. 14, the boundary on the left side is a line passing the midpoint between the edge of the projected portion of first-layer bit line 32a and the edge of first-layer bit line 32c, and extending parallel to first-layer bit line 32c. The boundary on the right side is a line passing the midpoint between the edge of the projected portion of first-layer bit line 32b and the edge of first-layer bit line 32d, and extending parallel to first-layer bit line 32d.
With the assumption as described above, the size in the row direction of the memory cell region of FIG. 14 will now be considered. Referring to FIG. 14, if S is a distance between the edges of the first-layer bit lines; M is a margin for the through-hole and the first-layer bit line; X is the size of the through-hole in the row direction; and W is the line width of the first-layer bit lines, then the size C1 of the memory cell region in the row direction can be expressed as follows: EQU C1=2S+3M+X+W
if 2M+X.gtoreq.W.
In FIG. 14, the pattern of the first-layer bit lines includes a portion projecting from both sides beyond the bit line width, around the region in which a through-hole is being disposed. FIG. 15 illustrates the pattern in the case where such projection is allowed only to one side.
With reference to FIG. 15, the boundary on the left side is a line passing the midpoint between the edges of first-layer bit lines 32e and 32c, and extending parallel to first-layer bit line 32c. The boundary on the light side is a line passing the midpoint between the edges of first-layer bit lines 32f and 32d, and extending parallel to first-layer bit line 32d.
In this case, the size C2 of the memory cell region in the row direction when 2M+X.gtoreq.W becomes as follows: EQU C2=2S+2M+X+W
The configuration shown in FIG. 15 enables the size of the memory cell region in the row direction to be decreased by M with respect to the configuration shown in FIG. 14.
As explained above, in FIGS. 14 and 15, the size of the memory cell in the row direction is limited by the size of the first-layer bit lines. If the size C1 or C2 of the memory cell region in the row direction is affected by the margin M for the through-hole and first-layer bit lines and the size X of the through-hole in the row direction, and thus exceeds the size C0 of the memory cell region in the row direction that is limited by the pattern underneath the first-layer bit lines, then it will become necessary to considerably increase the area of the memory cell array to ensure the size C1 or C2 in the row direction for every memory cell region.